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POWER MANAGEMENT Description
Three components make a complete system: any microcontroller, the SH3003, and a bypass capacitor. This low-cost system would consume very little power and have clock-frequency accuracy of 0.5%. A fourth component, a 32.768kHz crystal, raises the clock frequency accuracy to 0.0256% ( 256 ppm). The SH3003 can operate completely stand-alone, or under control of the microcontroller. A single-wire interface handles both bi-directional communications and the interrupt/wake-up signal from the SH3003. The SH3003 stores all configuration, calibration, parameters, and status information in a 36-byte bank of control registers. On reset, most of these are reloaded with defaults from the factory-set non-volatile memory. The microcontroller can change any settings on the fly. If some of the settings must remain fixed, a comprehensive set of write-protect bits is provided for several related groups of registers (with both permanent write-inhibit and lock/unlock capabilities). A backup power source may also be connected to the SH3003. The IC can directly accommodate 2/3-cell zinccarbon/alkaline, 2/3-cell mercury, 2/3/4-cell NiCd/NiMH, one cell Li/Li+ batteries, or a super cap. The programmable SH3003 MicroBuddy(R) (Buddy(R)) provides all mandatory microcontroller support functions: CPU Supervisor Clock Management System Real-Time Support Auxiliary Functions
MicroBuddy(R) Support IC for Microcontrollers
Features
Highly integrated * IC - 3mm x 3mm x 0.9mm, 16-lead MLP (QFN) package CPU Supervisor * Low VDD reset programmable from 2.3V to 4.3V * Watchdog timer with programmable time out periods * Both active-high and active-low reset outputs Clock Management System * Replaces high-frequency (HF) crystal or resonator * Programmable clock output from 32.768kHz to 16MHz * Speed shift between multiple clock frequencies * Adjustable spectrum spreading for EMI reduction * Directly supports microcontroller STOP function * Deep sleep with instantaneous auto-wakeup Real-Time Support * 179 year real-time clock, battery-backup capable * Dedicated 32.768kHz buffered clock output * Built-in trim for 32.768kHz oscillator to 4ppm * Programmable periodic interrupt/wakeup timer Auxiliary Functions * 4-byte (32-bit) scratchpad RAM, loaded on reset with factory-set value (zero or optional ID code) * All settings programmable in real time, defaults restored from nonvolatile memory on reset Operates from 2.3V to 5.5V * IDD < 850A /2MHz, < 3mA / 16MHz, <10A/ standby - IBUP < 2A / IBSB <50nA (battery back up/standby)
SH3003
Applications
Home automation and security Consumer products Portable/handheld computers Industrial equipment Any microcontroller-based product
May 23, 2006
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SH3003
POWER MANAGEMENT Typical Application Circuit
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V+ C Bypass VDD X IN X OUT GPIO with INT
16 15 14 13
N RESET
12 11 10 9
1 2 3 4
B
TM
Controller GND
SH3003
5 6 7 8
Typical Application Circuit with High Clock Accuracy
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SH3003
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended.
Parameter Supply voltages on VDD or VBAK relative to ground Input voltage on CLKIN, IO/INT, TEST Input voltage on CLKSEL Input current on any pin except VREG Input current on VREG Ambient operating temperature Storage Temperature IR Reflow temperature - SH3003IMLTR IR Reflow temperature - SH3003IMLTRT
Symbol VDD VIN1 VIN2 IIN1 IIN2 TOP TSTG TIRRT TIRRT
Min -0.5 -0.5 -0.5
Max 5.5 VDD + 0.5 VREG + 0.5 10 150
Units V V V mA mA C C C C
-40 -55
85 60 240 260
Electrical Characteristics
Parameter Case temperature Supply voltage Supply current, CLKOUT = 16 MHz(1) Supply current, CLKOUT = 8 MHz (1) Supply current, CLKOUT = 2 MHz(1) Standby current, 32.768kHz crystal(2) Standby current, 32.768kHz RC oscillator(2) Backup supply voltage(2) Backup current, 32.768kHz crystal(2) Backup current, 32.768kHz RC oscillator(2) Backup standby current(2)
Notes: 1) Assuming load on CLKOUT < 20pf 2) Assuming temperature < 60C (c)2006 Semtech Corp. 3 www.semtech.com
Symbol TOP VDD IDD IDD IDD ISB ISB VBAK IBUP IBUP IBSB
Min -40 2.3
Typ
Max +85 5.5 3
Units C V mA mA mA
Notes
1.8 0.9 8 10 2.3 5.5 2 8 50
A A V A A nA
CLK32 disabled CLK32 disabled
CLK32 disabled CLK32 disabled VDD > VBO
SH3003
POWER MANAGEMENT Electrical Characteristics (continued)
Crystal Oscillator
Parameter Crystal operating frequency CLK32 duty cycle Start-up time XIN/XOUT padding capacitance after power-up Minimum XIN/XOUT padding capacitance Maximum XIN/XOUT padding capacitance Padding capacitance resolution XIN switching threshold XIN to CLK32 delay CLK32 frequency stability (crystal-dependent) CLK32 cycle-to-cycle jitter CLK32 rise/fall time (10pF load) CLK32 logic output low (0.5mA load) CLK32 logic output high (0.5mA load) Symbol FOP DC TST CPUP CMIN CMAX CRES VTH TD FS J TRF VOL VOH -0.5 12.5 10 40 2 0.6 0.5 1 0.05 10 0.25 -0.25 0.5 25 Min Typ 32.768 75 3 Max Units kHz % secs pF pF pF pF V ppm/C s % ns V Ref VDD*
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*Note: VDD here is VDD during normal operation and VBAK during battery backup.
32.768kHz RC Oscillator
Parameter External 1M referenced nominal frequency Internal 1M referenced nominal frequency CLK32 duty cycle* Programmed frequency accuracy at 25C Absolute accuracy (temp. & supply external 1M) Absolute accuracy (temp. & supply internal 1M) Frequency temperature stability (ext. 1M) Frequency temperature stability (int. 1M) Power on start-up time CLK32 cycle-to-cycle jitter* Symbol FEXT FINT DC FST FDE FDI FSE FSI TST J 40 -1 2 3 100 200 70 0.1 Min Typ 32.768 32.768 60 +1 Max Units kHZ kHZ % % % % ppm/C ppm/C s %
*Note: After power-up, pin CLK32 is disabled, pin RREF is also disabled, and the oscillator is set to operate without the external reference resistor. (c)2006 Semtech Corp. 4 www.semtech.com
SH3003
POWER MANAGEMENT Electrical Characteristics (continued)
Programmable Reset
Parameter VDD switching threshold after power-up VDD switching threshold for min code VBO(MIN) VDD switching threshold for max code VDD threshold resolution VDD hysteresis Falling VDD threshold switch delay Threshold DAC settling time Minimum VDD for valid NRST and RST Symbol VBO(PUP) VBO(MIN) VBO(MAX) VRES VHYS Td TDAC VDD(MIN) 2.27 4.2 Min Typ 2.3 2.3 4.3 33 50 2.5 4 1 2.33 4.4 Max Units V V V mV mV s ms V
High-Frequency Oscillator (HFO)
Parameter Minimum operating freq. (start-up default = 16MHz) Maximum operating frequency Frequency resolution Programmed frequency accuracy at 25C Frequency drift over temperature and supply CLKOUT cycle-to-cycle jitter (spread spectrum off) Start-up time from standby Settling time to 0.1% after HF digitally-controlled oscillator (DCO) code change CLKOUT duty cycle Frequency temperature stability Short-term frequency stability Minimum spread spectrum range* Maximum spread spectrum range* CLKOUT rise/fall time (20pF load) CLKOUT logic output low (4mA load) CLKOUT logic output high (4mA load) Symbol FMIN FMAX FRES FST FDRIFT J TSTART TSETT DC FTS FS SS(MIN) SS(MAX) TRF VOL VOH -0.4 40 100 0.5 32 256 3 0.25 -0.25 0.4 10 60 0.5 0.1 2 16.8 -0.3 Min Typ 5.6 21 2 +0.3 Max 8 Units MHz MHz kHz % % % s s % ppm/C %/sec kHz kHz ns V Ref VDD
*Note: After power-up, spectrum spreading of the high-frequency oscillator is disabled. (c)2006 Semtech Corp. 5 www.semtech.com
SH3003
POWER MANAGEMENT Pin Configuration
CLK OUT CLK 32 CLK IN IO/INT
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Ordering Information
Device
Package
MLP 3x3mm, 16 pins MLP 3x3mm, 16 pins, lead-free SH3000 Evaluation Kit SH3000 Evaluation Kit User Guide SH3000 Reference Manual
SH3003IMLTR SH3003IMLTRT
12 11 10
16
15
14
13
VSS VREG VDD VBAK
1 2 3 4 5
TOP VIEW
TEST VSS RST NRST NRST
EVK-SH3000USB SH3000EK.pdf SH3000UM.pdf
T 6 7 8
9
XOUT
MLP 16: 3x3 16 LEAD
Pin Descriptions
Pin T 1 2 3 4 5 6 VSS VREG VDD VBAK XIN XOUT Power Power Power Power Analog In Analog Out Pin Name Type Thermal pad - connect to ground Ground, 0V - All VSS pins and TEST (VSS) pin must be connected together. Output of internal Voltage Regulator, 2.2V nominal. This pin can power external loads of < 5mA. If load is "noisy" it requires a bypass capacitor. May be left unconnected or used as a high logic level signal for CLKSEL pin. Main power supply, +2.3 to +5.5V Back-up power supply for real-time clock, +2.3 to +5.5V (+1.8 to +5.5V typical). This voltage can be higher or lower than VDD. Connect a backup battery or backup capacitor (with external recharge circuit). Connect to VDD if not used. Oscillator pins for optional external low frequency crystal, typically 32.768kHz crystal with nominal 12.5pF load cap. Keep open or connect to VSS if not used. A logic low level selects the internal 32.768kHz RC oscillator (CLKSEL tied to VSS). A high state on this pin selects the 32.768kHz crystal oscillator (CLKSEL is connected to VREG). The SH3003 always starts up using the internal 32.768kHz RC oscillator. If CLKSEL is high, the internal 32.768kHz clock switches to the crystal oscillator once it has stabilized, and RC oscillator is disabled for power conservation. Do not connect CLKSEL to any signals except VSS or VREG. CLKSEL must not be left open. Ground, 0V. All VSS pins and TEST (VSS) pin must be connected together. Pin Function
7
CLKSEL
Digital In
8
VSS
Power
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CLKSEL
VSS
XIN
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SH3003
POWER MANAGEMENT Pin Descriptions (continued)
Pin 9 Pin Name RREF Type Analog Pin Function Optional 1M external bias resistor for internal 32.768 kHz RC oscillator. Can be used to set, trim or modulate the internal RC oscillator. Keep open if not used. Active low system reset output. Asserted with a strong low state when a reset condition occurs. Weakly pulled to VDD internally when not active. This signal is valid for VDD as low as 1V. Keep open if not used. Active high system reset output. Asserted with a strong high state when a reset condition occurs. Weakly pulled to VSS internally when not active. This signal is valid for VDD as low as 1 V. Keep open if not used. Factory test enable. All VSS pins & TEST (VSS) pin must be connected together. Buffered internal 32.768 kHz clock, derived according to the CLKSEL pin setting. Pin uses backup power for the buffer when VDD is not present. When driving high, this signal is either at VBAK or VDD (if VDD is higher than the reset threshold). When enabled, this signal runs continuously independent of CLKOUT activity. Minimize the external load to reduce power consumption during backup operations. When disabled, this pin is driven to VSS. Keep open if not used. Serial communications interface and interrupt output pin. Pin is internally weakly pulled to opposite of programmed interrupt polarity. If interrupt is programmed to be active low, pin is weakly pulled to VDD when inactive. Keep open if not used. Clock activity sense input. Detects when target microcontroller enters stop mode (which disables its clock). Connect to the microcontroller's clock output or oscillator output pin. Connect to VSS when not used. CLKIN must not be left open. Programmable high frequency clock output. Connect to the target microcontroller's clock input or oscillator input pin. Keep open if not used. Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally.
10
NRST
Digital Out
11 12
RST TEST (VSS)
Digital Out Digital In
13
CLK32
Digital Out
14
IO/INT
I/O
15
CLKIN
Digital In
16 T
CLKOUT
Digital Out
Thermal Pad
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SH3003
POWER MANAGEMENT Block Diagram
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Microcontroller
VDD 32.768
KHZ
XIN
XOUT
RESET
I/O PIN
V+
CLKOUT
CLK32
2
3
13
16
CLKIN
VREG
VDD
15
VBAK
4 Regulators & Battery Back-up
VSS
Clock Driver & Start/Stop Logic Post-scaler HF Oscillator & FLL
Nonvolatile Memory Calibration & Default Settings
RST
1
VSS
8
XIN
Voltage Reference LF Oscillator XTAL Oscillator
VDD Monitor Watchdog
Reset Drivers & Logic
11
NRST
5
XOUT
10 Control Logic
TEST
6
CLKSEL
Real Time Clock Select Logic RC Oscillator SH3003 BuddyTM Periodic Interrupt / Wake-up Timer
12
7
RREF
Interrupt Serial I/O
IO/INT
9
14
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SH3003
POWER MANAGEMENT Application Information
The SH3003 is a single-chip support system for microcontrollers, microprocessors, DSPs and ASICs. It consists of four major functional blocks, each block having numerous enhancements over alternative solutions. The major modules are the CPU Supervisor, the Clock Management System, the Real-Time Support, and the Auxiliary functions. The entire chip is controlled by the set of internal registers and accessed via the single-pin serial interface. All of the settings, configuration, and calibration or operating parameters are programmable and re-programmable at any time. All of the parameters required for standalone operations are initialized on reset from the builtin factory-programmed nonvolatile memory. This allows the SH3003 to operate autonomously for most of its supervisory functions. The stand-alone operations do not require the use of the serial interface or any of the initialization and control operation, but without these, the full potential benefit of the SH3003 may not be realized. In the preferred configuration, where the SH3003 is tightly coupled to the target micro, the SH3003 offers an unprecedented level of design flexibility in clock and power usage management. The SH3003 is a particularly desirable integration because the built-in features interact and meld to produce more useful system level functions. For example, on power-up, the SH3003 can quickly release the reset lines on its CPU Supervisor module because the clock signal from the Clock Management System is guaranteed to be running and stabilized. An ordinary reset circuit must hold reset active for a long time to allow an unknown crystal to start up and stabilize. The SH3003 offers several ways to minimize system power consumption, such as allowing the target processor to enter deep sleep by stopping its clock completely, and to wake up as often as necessary with no external support. The clock can be programmed to start up at a given frequency, and software can adjust it dynamically to manage power consumption and different operating modes. Users should consider the interactions of the major functional blocks to gain the maximum advantage from the SH3003. The individual functional blocks are described in the following sections.
Default Start-Up Parameters While the operating parameters of the SH3003 are programmable by the host microcontroller at any time, the default start-up parameters and appropriate calibration values are programmed into the chip's nonvolatile memory at the factory. This enables the SH3003 to be used stand-alone or in an embedded application with minimal microprocessor intervention. Default start-up parameters for the SH3003 are: * * * * * Reset and VBO voltage level is 2.3V CLKOUT frequency is 16.0MHz CLK32 output is disabled Spread spectrum is disabled Internal RC oscillator is calibrated (to nominal frequency of 32768Hz
Internal load capacitors on the 32.768kHz crystal oscillator pins are set to 12.5pF.
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SH3003
POWER MANAGEMENT Application Information (continued)
CPU Supervisor The SH3003 has two supervisory functions that manage the reset of the target processor, a low VDD monitor (Brownout Detector) and a Watchdog Timer, see Figure 1. Both functions are integrated with the Clock Management System to provide a more complete system solution than stand-alone components. The SH3003 has both active high and active low reset output pins. Both are driven strong to the active state and weak to the inactive state. This eliminates the need for external pull-ups and allows various reset sources to be connected together in a wire-OR configuration. (This makes it simple to set up a manual reset circuit.) A set of flags in the register map indicates the source of the reset to the system software.
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Low VDD Reset The SH3003 drives the reset pins active whenever VDD is below the value of VBO, the brownout reset threshold, programmable from 2.3V to 4.3V in average steps of 33mV, see Table 1.
Parameter VBO for min code
Min 2.27
Typ 2.3
Max 2.33
Units V
(000000) VBO for max code (111111)
Step resolution
4.2
4.3 33
4.4
V mV
Table 1 The default VBO value is loaded on power-up from the factory-programmed non-volatile memory. It can be re-programmed at any time or it can be permanently protected from any changes by setting the VBO Lock flag or a writeprotect flag.
VDD
Noise Filter
RESET 32kHz PWROK
3
Reset Logic & Minimum Duration Timer
UNDERFLOW 1 0
VDD 20K
RST
11
NRST
20K
Temperature- 4.40 V VHIGH compensated Threshold
RESET CLKOUT
10 Watchdog Reload Control
Alternating Codes Logic 0x5A / 0xC3 From / To Serial I/O
Voltage Reference
Lock Logic
2.30 V
VLOW
D/A
Hysteresis 50mV TYP.
32 kHz
256
7-bit Down Counter
128
Load 7-bit Watchdog Timeout Value
6-bit Value
Write-once Initialization Logic
Mode
Figure 1. CPU Supervisor --- Low VDD / Brownout Detector, Watchdog, Reset logic & Drivers
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SH3003
POWER MANAGEMENT Application Information (continued)
Low VDD Reset (continued) On power up both the active-high and active-low reset signals are driven active. These outputs are typically valid for a VDD level of at least 0.5V, and guaranteed to be valid for a VDD level of 1.0V. The reset outputs remain active until VDD rises and stays above the level of (VBO + VHYST), where VHYST is a small fixed amount of hysteresis, nominally 50mV, added to prevent nuisance reset activations (when VDD slowly changes near the level of VBO and some noise or power glitching is present). At the level of (VBO + VHYST) the power supply is considered valid. In case of the initial power-up, the reset is then driven inactive once 6ms of valid power have elapsed. In the case of brownout, the reset is released after a delay of 6ms (but no less than 12ms from the beginning of the brownout). Such a fast reset is possible because the SH3003 provides a fast-starting clock that is free of crystal start-up time requirements. This gives the SH3003 an advantage over most external reset circuits, which must have a long reset pulse duration to accommodate long and unpredictable crystal start-up times. The SH3003 guarantees that a valid and stable clock is available 2ms before the reset signals are negated, so that internal synchronous reset and initialization of the target micro can proceed normally.
VBO + VHYST VBO
Since the clock is only active for the last 1 or 2ms of the reset interval, when VDD has already been valid for some time, energy savings are realized and the start-up of the whole system is made easier. The commonly used reset approach forces the processor to turn the oscillator on and to run at full speed (thus consuming full power) during the critical time when the (possibly depleted) battery is trying to raise VDD to an acceptable level. In contrast, the SH3003 allows the power source to charge the bypass capacitors and raise the level of VDD with little additional load. Only when power has stabilized is the target micro permitted to start expending energy. When a brownout event occurs, the SH3003 continues to provide the clock to the target processor, but at a reduced frequency between 500kHz and 1.0MHz. After a delay of 2ms this clock is stopped, automatically lowering the energy consumption of the whole system, (see Figure 2). A Noise Filter (see Figure 1, Page 10) prevents reset activations from noise and small power glitches on the VDD line. A typical behavior is shown in Figure 3 for the VDD level just above VBO and various amplitudes and durations of the negative-going spikes. When VDD is falling, both reset lines are guaranteed to activate within 5s from the time VBO is crossed over.
12 ms minimum
10
Duration Amplitude
VDD
1V
3-5 ms RST
6 ms
Duration, s
5
Guaranteed reset
Undefined
NRST
Guaranteed NO reset
1 ms CLKOUT Normal FOUT 2 ms 2 ms Reduced FOUT 0.5-1.0 MHz
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Am plitude, V
Figure 3. Response to negative voltage spikes
Figure 2. Operations of low VDD / Brownout Detector
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SH3003
POWER MANAGEMENT Application Information (continued)
Watchdog Timer The second circuit for supervising the processor is the watchdog timer. Whereas the low VDD/Brownout Detector monitors supply voltage, the watchdog timer monitors behavior. It is based on a programmable timer that must be restarted periodically by the host micro. If software fails to restart the timer, the watchdog resets the processor. Restarting the timer takes considerable processing, making it unlikely that it would occur accidentally, as might happen for a simple pin-strobe configuration of typical watchdog IC. The watchdog is disabled after reset occurs. It stays disabled until initialized by the host processor. The initialization requires the watchdog clock mode to be selected (see Figure 1) and the 7-bit time-out value to be set. As soon as the time-out is written, the watchdog begins operations and can not be stopped; also, the time-out value and or clock source can no longer be changed. The two clock sources available for the watchdog are the internal 32.768kHz clock and the CLKOUT signal. When operating from the 32.768kHz source, the time-out interval is programmable from 7.8125ms to one second with resolution of 7.8125ms. The internal 32.768kHz clock is running all the time, therefore the time-out duration is fixed and predictable. When operating from the CLKOUT signal the time-interval is programmable between 256 and 32768 cycles of CLKOUT with resolution of 256 cycles. The actual time-out duration is variable and depends both on the frequency of CLKOUT signal and the amount of time target micro spends in the STOP mode, when the CLKOUT signal is also stopped. These two clock modes, together with the programmable time-out value, allow the SH3003 exceptional flexibility, previously unattainable by existing discrete watchdog solutions. The watchdog timer is kept from timing out by periodic reload of the time-out value, triggered by a write of a code byte to the Watchdog Reload Register. As a further safety measure, there are two different and alternating code bytes that should be written to the same Watchdog Reload Register. The code values are 0x5A and 0xC3. The timer is reloaded after every write of a single code byte. The code byte should be written to the Watchdog Reload Register, or reset is activated when the watchdog timer expires. Also, reset is initiated immediately if the value of the code byte is incorrect or out of sequence. When the watchdog triggers the reset, its duration is 12ms. Using two separate software routines, each to write one of the code values, results in the highest level of system security. These routines must execute in the correct order. It is unlikely that runaway code could manage this. In addition, this design makes it difficult for the code to become stuck in a tight loop resetting the watchdog.
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SH3003
POWER MANAGEMENT Application Information (continued)
Clock Management System The SH3003 provides a flexible tool for creating and managing clocks, a versatile and accurate "any frequency" clock synthesizer (see Figure 4). It is capable of generating any frequency in the range of 62.5kHz to 16.0MHz, with worst-case resolution of 0.0256% (256ppm). The internal 32.768kHz clock can also be routed to the CLKOUT pin (and HF oscillator stopped for energy savings). The objectives, features, and behavior of the Clock Management System are aimed towards the systems that utilize a microcontroller, a microprocessor, a DSP or an ASIC. The SH3003 permits the automatic sensing of the intentions of the host processor, an industry first. The SH3003 shuts down its clock output when it senses that the host processor issued a STOP instruction. Subsequently, the SH3003 idles, consuming less than 10A. As soon as the host exits the STOP mode, the SH3003 instantaneously starts to supply a stable clock (< 2s wake-up). A typical system, constructed with a ceramic resonator or a crystal as the frequency determining element, must wait at least several hundred microseconds (for a resonator), or as much as 100ms or more (for a HF crystal), to re-start the oscillator. The SH3003 allows the response to and service of an event to finish with a speed previously unattainable for a simple microprocessor. A system with a traditional clock approach may be as much as 100x - 10,000x slower.
Clock Generator Operation The frequency synthesizer in the SH3003 is constructed from the 2:1 tunable 8.0 -16.0 MHz HF oscillator followed by a programmable "power-of-two" post-divider (see Figure 4). The Clock Source selector and the programmable postscale divider allow instantaneous switching between the 32.768kHz internal clock and divided-down HF oscillator output. There is no settling or instability when the switch occurs. This is a preferred method for clock control in computing systems, when the large ratio between high and low frequency of operations allows for correspondingly large and instantaneous savings in power consumption.
Clock Source 32.768 kHz FLL On
1
Clock On CLKOUT
Post-scaler (Divide by 1, 2, 4, 8, 16, 32, 64, 128) 18-bit DCO Code Register 8-bit Pseudo Random Noise Generator
0
Clock Buffer and Glue Logic HF Digitally Controlled Oscillator 8-16 MHz
16
CLKIN
15
Force DCO On
START/STOP
16
2048 Hz
Frequency Locked Loop Logic 13-bit Frequency Set value
Spectrum Spreading Controls
From / To Serial I/O
Figure 4. Simplified HF Oscillator System
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SH3003
POWER MANAGEMENT Application Information (continued)
Clock Generator Operation (continued) When the HF oscillator is operating alone, it can set the frequency of the clock on the CLKOUT pin to 0.025%, and maintain it to 0.5% over temperature. This compares favorable with the typical 0.5% initial clock accuracy and 0.6% overall temperature stability of ceramic resonators. The SH3003 replaces the typical resonator, using less space and providing better performance and functionality. The HF oscillator can also be locked to the internal 32.768kHz signal. The absolute accuracy and stability of the HF clock depends on the quality of the 32.768 kHz internally generated clock; the low-frequency (LF) Oscillator System is described later in this document. When the Real-Time Clock module of the SH3003 is used for highaccuracy timekeeping, an external 32.768 kHz crystal used as a reference for RTC provides excellent accuracy and stability for the Clock Management System. The SH3003 employs a Frequency Locked Loop (FLL) to synchronize the HF clock to the 32.768kHz reference. This architecture has several advantages over the common PLL (Phase Locked Loop) systems, including the ability to stop and re-start without frequency transients or instability, and with instant settling to a correct frequency. The conventional PLL approach invariably includes a LowPass Filter that requires a long settling time on re-start. The primary purpose of the FLL is the maintenance of the correct frequency while the ambient temperature is changing. As the temperature drift of the HF oscillator is quite small, any corrective action from the FLL system is also small and gradual, commensurate with the temperature variation. The FLL system in the SH3003 is unconditionally stable. To set a new frequency for the FLL, the host processor writes the 13-bit Frequency Set value. The resulting output frequency is calculated using simple formulas: [1] and [2] (reference frequency is 32.768kHz):
FOSC = 2048 Hz * (Frequency Set value + 1) [1] FOUT = FOSC / (Post-divider setting) [2]
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For example, a post-divider setting of /8 and the Frequency Set value of 4000 (0x0FA0) produce an output frequency of 1.024MHz.
Programmable Spectrum Spreading Most commercial electronic systems must pass regulatory tests in order to determine the degree of their Electromagnetic Interference (EMI) affecting other electronic devices. In some cases compliance with the EMI standards is costly and complicated. The SH3003 offers a technique for reducing the EMI. It can be a part of the initial design strategy, or it can be applied in the prototype stage to fix problems identified during compliance testing. This feature of the SH3003 may greatly reduce the requirements for radiofrequency shielding, and permits the use of simple plastic casings in place of expensive RFI-coated or metal casings. The SH3003 employs Programmable Spectrum Spreading in order to reduce the RF emissions from the processor's clock. There are five possible settings; please see Table 2 for operating and performance figures in the 8-16MHz range.
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SH3003
POWER MANAGEMENT Application Information (continued)
Programmable Spectrum Spreading (continued)
Setting Spreading Bandwidth kHz Peak EMI Reduction (guaranteed db) Peak EMI Reduction (measured db)
En 0 1 1 1 1
CFG1 x 0 0 1 1
CFG0 x 0 1 0 1
Off 32 64 128 256
0 -3 -6 -9 -12
0 -3 -7 -10 -15
Table 2 - EMI reduction with Spectrum Spreading
Spectrum Spreading is created by varying the frequency of the HF oscillator with a pseudo-random sequence (with a zero-average DC component). The Maximum-Length Sequence (MLS) 8-bit random number generator, clocked by 32.768kHz, is used. Only four, five, six, or seven bits of the generated 8-bit random number are used, according to the configuration setting. Maximum fluctuations of the frequency depend on the selected frequency range and the position within the range. Selecting the HF oscillator frequency to be near the high end of the range limits the peak variations to 0.1%, 0.2%, 0.4%, or 0.8% (corresponding to the configuration setting).
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SH3003
POWER MANAGEMENT Application Information (continued)
Special Operating Modes The SH3003 can operate stand-alone, without connections to the In and Out terminals of the host's oscillator. For example, a bank of SH3003 chips can generate several different frequencies for simultaneous use in the system, all controlled by a single micro (and possibly sharing one 32.768kHz crystal by chaining the CLK32 pin to XIN pin on the next device). In this case the CLKIN pin should be connected to VSS. The clock output on the CLKOUT pin is continuous; the correct operating mode is automatically recognized by the SH3003. A microcontroller may not have a STOP command. With the SH3003, this controller can do a "simulated" STOP by issuing an instruction to the SH3003 to stop the clock. This command is accepted only if the Periodic Interrupt / Wakeup Timer has started (otherwise, once the system is put to sleep, it would never wake up again). This mode of operations is only possible if the host processor is capable of correct operations with clock frequency down to zero, and keeps all of the internal RAM alive while the clock is stopped.
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Real Time Support The SH3003 has two support modules that are specifically designed for various real time support functions. They are the Real-Time Clock and the Periodic Interrupt / Wakeup Timer. Both of these units as well as other functions of the SH3003 depend on the internal 32.768kHz clock for accuracy. The SH3003 allows a trade-off between the cost of a system and its accuracy. For some devices, a single SH3003 without any support components provides sufficient accuracy. These units can operate with processor clock accuracy of 0.5% and the accuracy of the real-time system of 3%. At the other end of the spectrum, with one external component (a 32.768kHz crystal), the SH3003 can provide a processor clock accuracy of 256ppm (0.0256%) and the accuracy of the real-time system of 4ppm ( 0.0004%).
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SH3003
POWER MANAGEMENT Application Information (continued)
Low Frequency (LF) Oscillator System This module provides the 32.768kHz clock to all internal circuits and to the dedicated output pin, CLK32. If enabled, the CLK32 output continues normal operations when VDD is absent and backup power is available. When the power is first applied to the SH3003, the RC oscillator takes over. It supplies the 32.768 kHz clock for start-up and initialization. However, if the CLKSEL pin is set high, then the crystal oscillator is enabled. Once the crystal has started and stabilized, the internal 32.768 Hz clock switches to the very accurate crystal frequency; see Figure 5. Just like the VBO value for the Reset circuit, the default calibration values for the RC oscillator are loaded on power-up from the factory-programmed non-volatile memory. They can be re-programmed at any time or they can be permanently protected from any changes by setting the Lock flag or a write-protect flag. Factory calibration brings the frequency of the RC oscillator within % of the 32.768kHz for the internal reference resistor, and 2% for the external 1M 1% resistor, over the entire temperature and supply voltage range. The frequency of the RC oscillator can be tuned or modulated by varying the external reference resistor, which should be located as close as possible to RREF, pin 9. The crystal oscillator has the useful feature of adjustable load capacitors. It permits tuning of the circuit for initial tolerance of the crystal (often 20ppm) as well as an adjustment for the required load capacitance (with possible variations from the PCB layout). While the oscillator was designed for a crystal with a nominal load capacitance of 12.5pF, the circuit accommodates any value from ~7pF to 22pF (depending on parasitics of the layout). All of these corrections can be performed when the part is already installed on the PCB, in the actual circuit. The default value for load capacitance (12.5pF) loaded on power-up from the factory-programmed nonvolatile memory can be re-programmed at any time (following a secure process of unlocking the load capacitance value register and immediately writing a new setting), or it can be completely protected from any changes by a permanent writeprotect flag. This adjustment can set the frequency of the crystal oscillator to within 4ppm of the ideal value. As a reference, a typical 32.768kHz crystal changes its frequency 4ppm for a 10C change in temperature. Since the temperature characteristics of crystals are well known and stable, the host processor is free to implement an algorithm for temperature compensation of the crystal oscillator using the adjustable load capacitors, with resulting accuracy of 4ppm over the entire temperature range.
XIN
5
32.768 kHz Crystal 12.5 pF Load Capacitance VREG X-TAL RC XOUT
X-tal stable?
CLK32 ON CLK32 INTERNAL RREF ON
6
CLKSEL
7
RREF
13 RC Oscillator
Internal RREF Internal 32.768 kHz Clock
9
External Reference Resistor 1 M 1% or variable
VSS
8
VSS
Lock / Unlock Logic
4-bit Value
6-bit Value
4-bit Value
Lock Logic From / To Serial I/O
1 Figure 5. Simplified LF Oscillator System
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SH3003
POWER MANAGEMENT Application Information (continued)
Real-Time Clock Using the 4ppm, 32.768kHz clock from the LF oscillator, the Real-Time Clock module keeps time with a maximum error as low as two minutes per year. This compares favorably with a conventional error of two minutes per month for the typical RTC chip. The hardware of the Real-Time Clock is capable of 179-years of calendar operations (see Figure 6). All counting-chain values are loaded at the same time into corresponding registers when the Fractions register is read. All values from registers are loaded into the counting-chain when the Fractions register is written. The RTC continues normal operations when VDD is absent, if backup power is available.
Not authorized for release outside of Semtech - DRAFT
LSB
LOAD
32-bit Latch 32-bit Counter
MSB
Current Timer Value
32.768 kHz 128
1 Hz
RESET
256 Hz
32-bit Comparator 256 60 60 24
16-bit Counter
LOAD Fractions Seconds Minutes Hours
Interrupt Logic
IO/INT
14
Serial I/O 32-bit Latch
(BIN) LSB 0 - 255
(BCD) 0 - 59
(BCD) 0 - 59
(BCD) 0 - 23
Days (BIN) 0 - 65535
LSB
32-bit Time Interval
MSB
Figure 6. Real Time Clock and Periodic Interrupt / Wakeup timer
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SH3003
POWER MANAGEMENT Application Information (continued)
Periodic Interrupt/Wakeup Timer Simple and versatile, the Periodic Interrupt/Wakeup Timer can be used to create very accurate recurring interrupts for use by the host micro. With some minimal software support from the host processor, it can also be used to create alarms, with practically unlimited duration. While the timer is running, the host processor may be halted, consuming no energy. The interrupt wakes up the processor, which can perform the requisite task and go back to sleep, until the next periodic interrupt. This mode of operation can achieve extremely low average power consumption. A 32-bit counter clocked by 32.768kHz, producing a minimum interval of 30.5s and the maximum interval of 36.4 hours, creates the Timer. After reset, the timer is stopped until the new value for the time interval is written into the 4-byte Time Interval register. When the least significant byte (LSB) is written, the whole value is moved to the Time Interval latch, the counter is reset and starts to increment with the 32.768 kHz clock. When the 32-bit comparator detects a match, an interrupt is generated and the counter is reset and starts the next timing cycle. Although the counter cannot be written to, the current value from the counter can be read at any time. The whole 32-bit value is loaded into the 32-bit Current Timer Value latch when the least significant byte is read. This prevents errors stemming from the finite time between the readings of individual bytes of the current value. Auxillary Functions Scratchpad RAM Four bytes of general-purpose RAM reside on the SH3003. Voltage Regulator Pin VREG can be used as a nominal 2.20V reference voltage or a supply source for small loads (< 2mA). A bypass capacitor may be necessary between this pin and VSS if the load generates large current transients or a low ripple reference is required.
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SH3003
POWER MANAGEMENT Application Information (continued)
Interrupt and Serial Interface A single line is used to convey bi-directional information between the SH3003 and the processor, and as the interrupt line to the processor. The polarity of the interrupt signal is programmable. The SH3003 and the host microcontroller communicate using a single wire, bi-directional asynchronous serial interface. The bit rate is automatically determined by the SH3003. At the fastest possible rate, a read or write access of a single byte from the register bank takes 5s. The SH3003 contains thirty-six addressable registers located at 0x00-0x1F. Some of these registers are accessed through a page operation. Pin 14, IO/Int, is the serial communications interface and interrupt output pin. This pin is internally weakly pulled to the opposite of the programmed interrupt polarity. For example, if interrupt is programmed to be active low, this pin is weakly pulled to VDD when inactive. As shown in Figure 7, the SH3003 and the host communicate with serial data streams. The host always initiates communication. A data stream consists of the following (in this order): * 3-bit start field * 3-bit read/write code * 5-bit address field * 1 guard bit * 8-bit data field * 2 parity bits Plus, for write streams only: * 1 guard bit * 2 acknowledge (ACK) bits The 3-bit start field (1,0,1 or 0,1,0, depending on interrupt polarity) uses the middle bit to determine the bit period of the serial data stream. The 3-bit read/write code consists of 1,1,0 for a read, or 0,1,1 for a write. This protects against early glitches that might otherwise put the interface into an invalid read or write access mode. The 5-bit address field contains the address of the register. A single guard bit gives the interface a safe period in which to change data direction. The value of a guard bit does not matter. The 8-bit data field is written to (read from) the register. Two parity bits: The first parity bit is high when there are an odd number of bits in the read/write, address and data fields; the second parity bit is the inverse of the first. For write streams only, a guard bit is appended to the stream (to allow safe turnaround), and then two acknowledge bits, which are a direct copy of the parity bits, are driven back to the host to indicate a successful write access. Two guard bits are appended to the end of the access stream (read or write). The host can not start the next access before receiving these bits. The interface is self-timed based on the duration of the start bit field, and communication can take place whenever CLKout is active, either at 32.768kHz or at a higher frequency. If the host microcontroller is running synchronously to the CLKout generated by the SH3003 (which should generally be the case), then a minimum of four CLKout cycles per bit are required to maintain communication integrity. If the host's serial interface is asynchronous to CLKout, then a minimum of 52 cycles per bit are necessary. A maximum of 1024 CLKout cycles per bit field is supported. Table 3 displays the minimum and maximum bit periods for the serial communications for CLKout frequencies of 16 MHz, 8MHz, and 2MHz.
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SH3003
POWER MANAGEMENT Application Information (continued)
Interrupt and Serial Interface (continued)
Minimum Bit Period CLKOUT Frequency (host synchronous to CLKOUT) 16MHz 8MHz 2MHz 250ns 500ns 2s Minimum Bit Period (host Asynchronous to CLKOUT) 3.25s 6.5s 26s
Maximum Bit Period 63.9s 127s 511s
Table 3 - Minimum/Maximum Serial Bit Timing
Interrupt Interface The serial communications line to the SH3003 (Pin 14, IO/Int) also serves as the interrupt to the host microcontroller. The polarity of the interrupt is software programmable using the interrupt polarity bit (bit 6) of the IPol_RCtune register (R0x11). This pin is asserted for four cycles of CLKout, and then returns to the inactive state. The interrupt line is used by the Periodic Interrupt/Wake-up Timer to interrupt the host when it reaches its end of count.
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SH3003
POWER MANAGEMENT Application Information (continued)
Not authorized for release outside of Semtech - DRAFT
IO/INT Timing Scenarios
1. INT disabled, uP initiates write access. Active high interrupt.
uBuddyIOOut uPIOOut CombinedIO State
Idle Prestart Start PostStart ACK0 ACK1
A0 A0 RW0 RW1 RW2
... ... ...
A4 A4
XXX
D0 D0 D0
D7
P0 P0 P0
P1 P1 P1
XXX XXX
XXX
... ...
D7 D7
ACK0
ACK1
A0
A4
Guard0
Guard1
ACK0
ACK1
Guard2
Guard3
Idle
2. INT active (high), uP initiates write access
uBuddyIOOut uPIOOut CombinedIO State
Idle IN T Pendin g-start Prestart Start PostStart ACK0 ACK1
If the interrupt did not get cleared, then it will activate again here
A0 A0 RW0 RW1 RW2
... ... ...
A4 A4
XXX
D0 D0 D0
D7
P0 P0 P0
P1 P1 P1
XXX XXX
XXX
... ...
D7 D7
ACK0
ACK1
A0
A4
Guard0
Guard1
ACK0
ACK1
Guard2
Guard3
IN T
Pendin g-start
3. INT active (low), uP initiates write access
uBuddyIOOut uPIOOut CombinedIO State
Idle IN T Pendin g-start Prestart Start PostStart ACK0 ACK1
If the interrupt did not get cleared, then it will activate again here
A0 A0 RW0 RW1 RW2
... ... ...
A4 A4
XXX
D0 D0 D0
D7
P0 P0 P0
P1 P1 P1
XXX XXX
XXX
... ...
D7 D7
ACK0
ACK1
A0
A4
Guard0
Guard1
ACK0
ACK1
Guard2
Guard3
IN T
Pendin g-start
4. INT disabled, uP initiates read access
uBuddyIOOut uPIOOut CombinedIO State
Idle Prestart Start PostStart
D0 A0 A0 RW0 RW1 RW2
... ... ...
D7
P0
P1
... ... ...
A4 A4
XXX
XXX
D0 D0
D7 D7
P0 P0
P1 P1
A0
A4
Guard0
Guard2
Guard3
Idle
Figure 7. Serial Communication Timing Diagram
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SH3003
POWER MANAGEMENT Typical Characteristics
Free Running HF DCO Frequency Deviation over Temperature for All Frequencies
4000
2000
0 -60 -40 -20 -2000 0 20 40 60 80 100 120 140
ppm Deviation
-4000
-6000
-8000
-10000
-12000
-14000
-16000
Temp. C
Internal 32.768 kHz Oscillator Frequency over Temperature
33400
33200
33000
Frequency (Hz)
32800
32600
32400
32200
32000
31800 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (C)
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SH3003
POWER MANAGEMENT Typical Characteristics (continued)
Not authorized for release outside of Semtech - DRAFT
32.768 kHz Crystal Oscillator Frequency Deviation over Temperature
50
0 -60 -40 -20 0 20 40 60 80 100 120
ppm Deviation
-50
-100
-150
-200
Temperature (C)
Battery Backup Current over Temperature (VBAK = 3 V)
18
16
14
12
VBAK Current (A)
10
8
6 Internal 32.768 kHz Crystal 32.768 kHz 4
2
0 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (C)
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SH3003
POWER MANAGEMENT Typical Characteristics (continued)
Standby Current over Temperature (VDD = 5 V)
25.0
20.0
VDD Current (A)
15.0 Crystal 32.768 kHz Internal 32.768 kHz 10.0
5.0
0.0 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (C)
Standby current over VDD (Temp. = 25C)
10
9
8
VDD Current (A)
7 Crystal 32.768 kHz Internal 32.768 kHz 6
5
4 2.5 3 3.5 4 4.5 5 5.5
VDD (V)
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SH3003
POWER MANAGEMENT Typical Characteristics (continued)
Not authorized for release outside of Semtech - DRAFT
VDD Current vs CLKOUT Frequency (VDD = 5.5 V, Temp. = 25C)
3500
3000
2500
VDD Current (A)
2000
1500
1000
500
0 0 2 4 6 8 10 12 14 16 18
Frequency (MHz)
Operating VDD Current over VDD (CLKOUT = 16 MHz, Temp = 25C)
3200
3000
2800
VDD Current (A)
2600
2400
2200
2000 2.5
3
3.5
4
4.5
5
5.5
VDD (V)
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SH3003
POWER MANAGEMENT Typical Characteristics (continued)
Free Running HF DCO Short Term Frequency Stability (CLKOUT = 8 MHz)
300
200
100
ppm Deviation
0 -500 -100 500 1500 2500 3500 4500 5500 6500
-200
-300
-400
Time (seconds)
FLL Locked HF DCO Jitter over Jitter Bandwidth (CLKOUT = 12.8 MHz)
100000
10000
rms Jitter (ps)
1000
100
10 0.1 1 10 100 1000 10000 100000
Jitter Bandwidth (kHz)
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SH3003
POWER MANAGEMENT Outline Drawing - MLP 3 x 3 mm 16 pins
Not authorized for release outside of Semtech - DRAFT
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SH3003
POWER MANAGEMENT Land Pattern - MLP 3 x 3 mm 16 pins
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SH3003
POWER MANAGEMENT
Not authorized for release outside of Semtech - DRAFT
Copyright (c)2002-2006 Semtech Corporation. All rights reserved. Semtech, the Semtech logo, MicroBuddy, Buddy, and B are marks of Semtech Corporation. All other marks belong to their respective owners. Changes may be made to this product without notice. Customers are advised to obtain the latest version of the relevant information before placing orders. LIMITED LICENSE GRANTED: NO WARRANTIES MADE This specification is provided "as is" with no warranties whatsoever including any warranty of merchantability, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Any suggestions or comments by Semtech concerning use of this product are opinion only, and Semtech makes no warranty as to results to be obtained in any specific application. A license is hereby granted to reproduce and distribute this specification for internal use only. No other license, expressed or implied to any other intellectual property rights is granted or intended hereby. Authors of this specification disclaim any liability, including liability for infringement of proprietary rights, relating to the implementation of information in this specification. Authors of this specification also do not warrant or represent that such implementation(s) will not infringe such rights.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
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